1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device including nonvolatile memories.
2. Description of the Related Art
Nowadays, an electrically erasable programmable read only memory (E.sup.2 PROM) of flash type (flash memory hereafter) is known as memory where data is able to be rewritten by using electricity.
The flash memory having a control gate electrode, a floating gate electrode, a source and a drain is characterized in that data stored in the floating gate can be electrically erased using a thinner gate insulating layer between the floating gate and the source or drain.
A conventional method for manufacturing this flash memory will be described below.
Referring to FIG. 1A, an entire surface of a silicon substrate 2 is oxidized to form a silicon oxide layer 4 on the silicon substrate 2.
Referring to FIG. 1B, field oxide layers 10 are formed in the entire surface of the silicon oxide layer by Local Oxidation of Silicon (LOCOS) technique to divide the substrate 2 into the plural insulated islands 12.
The substrate 2 is subjected to a injection step to adjust conductivity of what is to be channel regions.
The resulting substrate 2 is subjected to a heat treatment to form the surface of the insulated islands 12 into the tunnel oxide layer 14. A first polysilicon layer 16 is applied on the resulting substrate 2 using chemical vapor deposition (CVD) technique as shown in FIG. 1C.
The entire first polisilicon layer 16 is ion implanted with phosphorus thereby making the first polisilicon layer 16 N+ type.
Referring to FIG. 1D, thereafter on the first polysilicon layer 16 is formed a ONO layer 18 comprised of an oxide layer, a nitride layer and an oxide layer, a second polysilicon layer 20 is formed on the ONO layer 18 using the CVD technique. Similarly, phosphorus is ion-implanted and thereby making the second polysilicon layer 20 N+ type.
The resulting substrate 2 is subjected to a etch using a resist pattern as a mask to form a control gate electrode 26, an intervene insulating layer 24 and a floating gate 22.
Thereafter, what is to be a drain, and a surface of the control Gate electrode in side of drain are covered with a resist 30. Phosphorus is ion-implanted in such a direction as shown an arrow mark 32 using the resist 30 as a mask so that a region 38 of N- type may be created in the surface of silicon substrate 2 as shown in FIG. 2B. Then, after removing the resist 30, arsenic is implanted into the entire surface of substrate 2 with a low dosage of 2.times.10.sup.15 per cm.sup.2 so that a source comprised of the region 38 and a N+ type region 36, and a drain 40 of N+ type may be formed.
At last, the resulting substrate 2 is subjected to a step for protective layers, a wiring step and passivation step to complete the flash memory.
The flash memory as manufactured in the above fashion is used as a memory circuit having memory cells arrayed in rows by column as shown in FIG. 3. Referring to FIG. 3, in order to write data into a memory cell C11 which is to be desired, a high positive voltage is applied to a word line W1, a high positive voltage is applied to a bit line B1 and a voltage of 0 volts is applied to all of a source line S, a bit line B2 and a word line W2. At that time some of hot electrons develop by the drain 40 and then tunnel the tunnel oxide layer 14 acted as electric barrier, and enter into the floating Gate 22. The memory cell C11 in this state referred to as memory cell in "write state".
However, the above-mentioned flash memory has a problem with "wrong erasing" at writing operation.
Specifically, referring to the memory cell C13 at writing operation, the floating gate 22 is in a potential of 0 volts and the drain 40 is in a positive potential of the high voltage because the voltage of 0 volts is applied to the word line W2 and the positive high voltage is applied to the bit line B1. Meanwhile, the dosage of phosphorous is high in the entire first polysilicon layer 22. Therefore, the floating gate 22 has its own high conductivity, which lead to the fact that a rate of partial pressure to the tunnel oxide layer 14 is large. As the result of this, in the memory cell C13 electrons in the floating gate 22 may be drawn into the drain due to power of electric field. Thus, during the writing operation, data is erroneously erased from the memory cell C13.
To overcome this problem, there is an idea of lowering the dosage of phosphorous in the floating gate 22. However, a memory circuit made using this idea has a bad fact in that it takes a long time to erase a desired memory cell. That is, because decreasing the dosage of phosphorous decreases the rate of the partial pressure to the tunnel oxide layer 14, and the power of an electric field between the floating gate 22 and the source 36, 38 is weak.
Also, the above-mentioned flash memory has another problem. "Oxide ledge" occurs between the first polysilicon layer 22 and the tunnel oxide layer 14 because the first polysilicon has phosphorous of a high dosage. This "oxide ledge" cause a problem with "wrong erasing" due to a margin of electric field between the floating gate 22 and the source 36, 38 developed when data is erased from the flash memory cells.